Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees of freedom to control electronic devices. In particular, the behavior of graphene's charge carriers in response to potentials from charged Coulomb impurities is predicted to differ significantly from that of most materials. Scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) can provide detailed information on both the spatial and energy dependence of graphene's electronic structure in the presence of a charged impurity. The design of a hybrid impurity-graphene device, fabricated using controlled deposition of impurities onto a back-gated graphene surface, has enabled several novel methods for controllably tuning graphene's electronic properties. Electrostatic gating enables control of the charge carrier density in graphene and the ability to reversibly tune the charge and/or molecular states of an impurity. This paper outlines the process of fabricating a gate-tunable graphene device decorated with individual Coulomb impurities for combined STM/STS studies. These studies provide valuable insights into the underlying physics, as well as signposts for designing hybrid graphene devices.