Search research articles

ABOUT JoVE

Overview Leadership Blog JoVE Help Center

AUTHORS

Publishing Process Editorial Board Scope & Policies Peer Review FAQ Submit

LIBRARIANS

Testimonials Subscriptions Access Resources Library Advisory Board FAQ

RESEARCH

JoVE Journal Methods Collections JoVE Encyclopedia of Experiments Archive

EDUCATION

JoVE Core JoVE Business JoVE Science Education JoVE Lab Manual Faculty Resource Center Faculty Site

Terms & Conditions of Use

Related Concept Videos

MOS Capacitor

MOS Capacitor

A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by

Same author

The impact of COVID-19 social isolation and reduced microbial exposure on the immune system in children: a retrospective study.

PeerJ·2026

Same author

Electric field tunable coupling strength and quantum metric hot spots in a moiré flatband superconductor.

Nature communications·2026

Same author

Ferroelectric-Tunable Quantum Nonlinearity of Chiral Bloch Electrons in a Moiré System.

Nano letters·2026

Same author

Top-Gated Monolayer MoS<sub>2</sub> Transistors on Growth Substrate by One-Step Integration of High-κ Dielectrics and Low-Resistance Bilayer Contacts.

Nano letters·2026

Same author

Author Correction: Wafer-scale high-κ HfO<sub>2</sub> dielectric films with sub-5-Å equivalent oxide thickness for 2D MoS<sub>2</sub> transistors.

Nature communications·2026

Same author

Wafer-scale high-κ HfO<sub>2</sub> dielectric films with sub-5-Å equivalent oxide thickness for 2D MoS<sub>2</sub> transistors.

Nature communications·2026

Search research articles

Related Experiment Video

Updated: Mar 31, 2026

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

Nanographene charge trapping memory with a large memory window.

Jianling Meng¹, Rong Yang, Jing Zhao

¹Beijing National Laboratory for Condensed Matter Physics and Institute of Physics, Chinese Academy of Science, Beijing 100190, People's Republic of China.

|October 23, 2015

Summary

High-density nanographene fabrication enhances charge trapping memory. Plasma etching creates more sites, enabling a large memory window and faster speeds for next-gen electronics.

More Related Videos

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

Published on: June 18, 2013

Gradient Echo Quantum Memory in Warm Atomic Vapor

Gradient Echo Quantum Memory in Warm Atomic Vapor

Published on: November 11, 2013

Related Experiment Videos

Last Updated: Mar 31, 2026

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

Published on: June 18, 2013

Gradient Echo Quantum Memory in Warm Atomic Vapor

Gradient Echo Quantum Memory in Warm Atomic Vapor

Published on: November 11, 2013

Area of Science:

Materials Science
Nanotechnology
Electronics Engineering

Background:

Nanographene shows potential for charge trapping memory applications.
High density of nanographene is crucial for high charge trapping capacity.
Current limitations exist in achieving high-density nanographene for memory devices.

Purpose of the Study:

To develop a fabrication strategy for high-density nanographene for charge trapping memory.
To achieve a large memory window and improved performance in nanographene-based memory.
To explore plasma etching as a method for nanographene isolation and defect engineering.

Main Methods:

Fabrication of continuous nanographene film via direct growth.
Isolation of nanographene into high-density islands using plasma etching (argon or oxygen).
Characterization of memory properties including memory window, program/erase speed, and endurance.

Main Results:

Achieved high-density nanographene with abundant defects and edges through plasma etching.
Demonstrated nanographene charge trapping memory with a large memory window of ~9 V at ±8 V sweep voltage.
Observed fast program/erase speeds (~1 ms) and robust endurance (>1000 cycles).

Conclusions:

The developed plasma etching method effectively creates high-density nanographene for memory applications.
High-density nanographene memory exhibits superior performance compared to directly grown isolated islands.
This approach offers a promising alternative for downscaling memory technology beyond current flash memory capabilities.