Fully parallel write/read in resistive synaptic array for accelerating on-chip learning.

Area of Science:

• Neuromorphic engineering
• Materials science
• Computer architecture

Background:

• Emerging neuro-inspired computing paradigms aim to overcome von Neumann architecture limitations for complex AI tasks.
• Cross-point array architectures with synaptic devices are crucial for on-chip implementation of learning algorithms.

Purpose of the Study:

• To fabricate silicon-process-compatible synaptic devices for efficient neuromorphic computing.
• To design and demonstrate a fully parallel write scheme for accelerating training in cross-point arrays.
• To evaluate the performance and accuracy of the proposed architecture for handwritten digit recognition.

Main Methods:

• Fabrication of forming-free Ta/TaOx/TiO2/Ti synaptic devices with over 200 tunable conductance states.
• Design and experimental demonstration of a novel fully parallel write scheme in a small-scale crossbar array.
• Array-level simulation incorporating realistic device variations for MNIST handwritten digit recognition.

Main Results:

• Synaptic devices exhibited continuous tuning of >200 conductance states with identical programming pulses.
• The fully parallel write scheme demonstrated a speed-up of >30x and >30x energy efficiency improvement compared to row-by-row schemes.
• Simulations achieved ~95% recognition accuracy on MNIST, comparable to software-based sparse coding.

Conclusions:

• The developed synaptic devices and parallel write scheme offer a promising approach for efficient on-chip AI training.
• The proposed cross-point array architecture significantly enhances speed and energy efficiency for neuromorphic computing applications.
• The architecture demonstrates high accuracy for complex tasks like handwritten digit recognition, validating its potential beyond traditional computing.