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Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices

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Stretchable Si Logic Devices with Graphene Interconnects.

Wonho Lee¹, Houk Jang¹, Bongkyun Jang²

¹School of Electrical and Electronic Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul, 120-749, South Korea.

Small (Weinheim an Der Bergstrasse, Germany)

|October 29, 2015

Summary

This summary is machine-generated.

Ultrathin silicon integrated circuits with graphene interconnects maintain electrical performance under strain. Graphene protects silicon devices from over 10% strain by concentrating stress on interconnects.

Keywords:

graphene interconnects single crystals, Si nanomembranes stretchable devices, logic circuits stretchable transistors transfer printing

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Area of Science:

Materials Science
Electrical Engineering
Nanotechnology

Background:

Developing stretchable electronics requires robust interconnects that maintain performance under mechanical stress.
Traditional interconnects often fail under strain, limiting the application of flexible integrated circuits.

Purpose of the Study:

To demonstrate stretchable integrated circuits using ultrathin silicon transistors and multilayer graphene interconnects.
To evaluate the strain resilience of silicon integrated circuits protected by graphene.

Main Methods:

Fabrication of integrated circuits with ultrathin silicon transistors.
Integration of multilayer graphene as interconnects between silicon components.
Mechanical testing of the integrated circuits under varying degrees of strain.

Main Results:

Successful demonstration of stretchable integrated circuits comprising ultrathin silicon transistors and graphene interconnects.
Graphene interconnects effectively maintained the electrical performance of the integrated circuits under applied strain.
Silicon active devices were stably protected against strains exceeding 10% due to strain concentration on graphene.

Conclusions:

Multilayer graphene serves as a highly effective component for creating strain-resilient integrated circuits.
The proposed architecture enables robust silicon-based electronics for applications requiring significant mechanical flexibility.