Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip.

Area of Science:

• Computer Engineering
• Fault-Tolerant Systems
• VLSI Design

Background:

• Distributed clock generation in Systems-on-Chip (SoCs) is critical for system operation.
• Existing systems often struggle with transient and permanent faults, impacting reliability.
• Mathematical verification of fault-prone systems at the component level is complex.

Purpose of the Study:

• To implement a novel distributed clock generation scheme for SoCs.
• To achieve fault tolerance against unbounded transient and numerous permanent faults.
• To develop a verifiable approach for high-level properties of fault-prone systems.

Main Methods:

• Devised self-stabilizing hardware building blocks.
• Utilized a hybrid synchronous/asynchronous state machine for metastability-free transitions.
• Developed a comprehensive modeling approach for mathematical verification of low-level components and high-level properties.

Main Results:

• First implementation of a distributed clock generation scheme with high fault tolerance.
• Successful mathematical verification of high-level synchronization properties from basic components.
• Prototype implementation in VHDL, evaluated using Petrify and synthesized for FPGA.

Conclusions:

• The proposed approach provides robust fault recovery for SoC clock generation.
• Enables mathematically verifiable, high-level properties of fault-prone systems at manageable complexity.
• Demonstrates a significant advancement in designing reliable and verifiable integrated circuits.