An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay...

Area of Science:

• Digital communication systems
• VLSI design
• Error correction coding

Background:

• Convolutional codes are essential for Forward Error Correction (FEC) in digital communications.
• Viterbi decoders are crucial for decoding convolutional codes, balancing speed and power efficiency.
• Optimizing Very Large Scale Integration (VLSI) parameters is key for modern digital systems.

Purpose of the Study:

• To reduce the power consumption of Viterbi decoders using asynchronous design techniques.
• To evaluate the performance of asynchronous Viterbi decoders across different constraint lengths and VLSI technologies.
• To compare the power efficiency and speed of asynchronous versus synchronous Viterbi decoder designs.

Main Methods:

• Implementation of asynchronous Viterbi decoder modules based on Quasi Delay Insensitive (QDI) templates like Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB).
• Simulation and verification of the asynchronous design using Tanner Spice (TSPICE).
• Testing across multiple Taiwan Semiconductor Manufacture Company (TSMC) process nodes (0.25µm, 65nm, 180nm).

Main Results:

• The proposed asynchronous Viterbi decoder design demonstrates a power reduction of 25.21% compared to synchronous designs.
• The asynchronous design achieves a high operating speed of 475 MHz.
• The effectiveness of asynchronous design is validated across various VLSI technologies.

Conclusions:

• Asynchronous design methodologies offer significant power savings for Viterbi decoders in VLSI.
• The proposed QDI-based asynchronous approach provides a viable alternative to synchronous designs for high-speed, low-power communication systems.
• This research contributes to the development of more energy-efficient digital communication hardware.