Gate Modulation of Threshold Voltage Instability in Multilayer InSe Field Effect Transistors

Area of Science:

• Materials Science
• Condensed Matter Physics
• Nanotechnology

Background:

• Field-effect transistors (FETs) based on multilayer Indium Selenide (InSe) are promising for next-generation electronics.
• The performance stability of these InSe FETs under operational stress is a critical factor for practical applications.

Purpose of the Study:

• To investigate the modulation of threshold voltage instability in back-gated multilayer InSe FETs.
• To analyze the influence of gate bias stress parameters on the performance stability of InSe FETs under ambient conditions.

Main Methods:

• Applying gate bias stress to multilayer InSe FETs.
• Monitoring changes in threshold voltage and on-current.
• Analyzing the effects of gate bias polarity, stress time, and sweep rate.

Main Results:

• Negative bias stress increased on-current and shifted threshold voltage negatively; positive bias stress showed opposite effects.
• The magnitude of gate bias stress effects was dependent on stress duration and sweep rate.
• Observed instability was attributed to surface charge trapping involving adsorbed oxygen and water molecules.

Conclusions:

• Gate bias stress significantly modulates the performance instability of back-gated multilayer InSe FETs.
• The findings provide insights into the surface charge trapping mechanisms affecting InSe devices.
• This research offers guidance for designing stable and reliable InSe nanoelectronic and optoelectronic devices.