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Memcomputing NP-complete problems in polynomial time using polynomial resources and collective states.

Fabio Lorenzo Traversa1, Chiara Ramella2, Fabrizio Bonani2

  • 1Department of Physics, University of California, San Diego, La Jolla, CA 92093, USA. ; Department of Electronics and Telecommunications, Politecnico di Torino, 10129 Turin, Italy.

Science Advances
|November 25, 2015
PubMed
Summary
This summary is machine-generated.

Memcomputing, a brain-inspired computation paradigm, solves NP-complete problems efficiently using interacting memory cells. This novel approach demonstrates a proof-of-concept architecture for solving the subset sum problem in a single step.

Keywords:
Electronic circuitsMecomputingMemorycomputingmemory devicesnon Turing Machine

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Area of Science:

  • Computer Science
  • Computational Theory
  • Microelectronics

Background:

  • Memcomputing is a novel non-Turing computational paradigm.
  • It utilizes interacting memory cells (memprocessors) for integrated information storage and processing.
  • Memcomputing machines possess computational power equivalent to nondeterministic Turing machines.

Purpose of the Study:

  • To demonstrate an experimental memcomputing architecture.
  • To solve an NP-complete problem (subset sum) using this architecture.
  • To showcase the feasibility of memcomputing in a laboratory setting.

Main Methods:

  • Developed a memcomputing architecture using standard microelectronic technology.
  • Designed the architecture to solve the NP-complete subset sum problem.
  • Employed interacting memory cells for parallel processing and information compression.

Main Results:

  • The memcomputing architecture solved the subset sum problem in a single step.
  • The number of memprocessors scaled linearly with the problem size.
  • This represents the first proof of concept for a machine operating on the collective state of memory cells.

Conclusions:

  • Memcomputing offers a powerful alternative to traditional von Neumann architectures for specific computational tasks.
  • The demonstrated architecture is easily realizable, paving the way for future memcomputing devices.
  • Noise limitations necessitate error-correcting codes for scaling, but the core concept is validated.