A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

Area of Science:

• Electrical Engineering
• Sensor Technology
• Integrated Circuits

Background:

• CMOS image sensors (CIS) require efficient analog-to-digital converters (ADCs) for high-performance imaging.
• Reducing noise and conversion time in ADCs is critical for low-noise CIS applications.

Purpose of the Study:

• To present a fast multiple sampling method for low-noise CMOS image sensor applications.
• To improve the performance of column-parallel successive approximation register (SAR) ADCs.

Main Methods:

• Implemented a 12-bit SAR ADC with a novel multiple sampling technique.
• Utilized a 10-bit capacitor digital-to-analog converter (DAC) with scaled reference voltages to reduce ADC area.
• Developed an up/down counter-based digital processing logic for complex calculations.

Main Results:

• Reduced A/D conversion time from 1.2 μs to 0.45 μs per pixel.
• Decreased random noise from 848.3 μV to 270.4 μV.
• Achieved a dynamic range of 68.1 dB and a signal-to-noise ratio (SNR) of 39.2 dB.

Conclusions:

• The proposed multiple sampling method effectively reduces conversion time and noise in SAR ADCs for CIS.
• The fabricated 256 × 128 pixel array CIS demonstrates the practical viability of the proposed technique.
• This method offers a significant improvement for low-noise, high-speed image sensing applications.