An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data...

Area of Science:

• Computer Engineering
• Artificial Intelligence
• VLSI Design

Background:

• Deep learning algorithms excel in pattern recognition but require substantial computational resources, limiting their use on personal devices.
• The growing demand for on-device AI necessitates efficient hardware solutions for deep learning inference.
• Existing solutions often rely on high-cost, power-intensive platforms like servers or GPUs.

Purpose of the Study:

• To present a System-on-Chip (SoC) implementation enabling deep learning applications on low-cost, portable devices.
• To develop an energy-efficient processor for real-time deep learning inference tailored for wearable systems.
• To overcome the limitations of conventional massively-parallel architectures with a task-flexible approach.

Main Methods:

• Designed and fabricated a 2.5 mm × 4.0 mm deep learning/inference processor using 65 nm 8-metal CMOS technology.
• Employed a task-flexible architecture with multiple parallelism to handle complex deep learning functions, specifically convolutional deep belief networks.
• Optimized the design for low power consumption on battery-powered platforms.

Main Results:

• Achieved 411.3 GOPS peak performance and 1.93 TOPS/W energy efficiency.
• Consumed 185 mW average power and 213.1 mW peak power at 200 MHz and 1.2 V.
• Demonstrated 2.07× higher energy efficiency compared to state-of-the-art solutions.

Conclusions:

• The implemented SoC enables efficient deep learning inference on wearable and portable devices.
• The task-flexible architecture provides a cost-effective and energy-efficient solution for on-device AI.
• This work significantly advances the feasibility of complex deep learning applications in resource-constrained environments.