Triplet Spike Time-Dependent Plasticity in a Floating-Gate Synapse.

Area of Science:

• Neuroscience and Neuromorphic Engineering
• Integrated Circuit Design for AI

Background:

• Synaptic plasticity is crucial for neural network learning, with spike-timing-dependent plasticity (STDP) rules modifying synaptic strength based on spike timing.
• The commonly used doublet STDP (D-STDP) has limitations in replicating biological experimental results.
• Triplet STDP (T-STDP), considering spike triplets, has been proposed to better explain biological observations.

Purpose of the Study:

• To describe a compact synapse implementation using a single floating-gate (FG) transistor for nonvolatile weight storage.
• To demonstrate the triplet STDP (T-STDP) learning rule using this FG synapse.
• To present a mathematical procedure for obtaining control voltages for T-STDP in FG devices.

Main Methods:

• Implementation of a synapse using a single floating-gate (FG) transistor for nonvolatile weight storage.
• Demonstration of the T-STDP learning rule by modulating drain voltages based on spike triplets.
• Fabrication of an FG synapse in a TSMC 0.35-μm CMOS process and measurement of its performance.
• Simulation of very large scale integration (VLSI) compatible drain voltage waveform generator circuits.

Main Results:

• Successful demonstration of T-STDP learning rule implementation using a compact FG synapse.
• Measurement results from the fabricated FG synapse support the theoretical framework.
• Simulation results indicate the feasibility of VLSI implementation for T-STDP waveform generation.

Conclusions:

• A compact, nonvolatile FG synapse can effectively implement the T-STDP learning rule.
• The proposed method provides a viable pathway for advanced, biologically plausible learning in neuromorphic systems.
• The study validates the T-STDP theory with experimental data and suggests practical VLSI integration strategies.