A 1024-Channel 0.8V 23.9-nW/Channel Event-Based Compute In-Memory Neural Spike Detector.

Area of Science:

• Neurotechnology
• Biomedical Engineering
• Computer Engineering

Background:

• High data rates and power consumption are critical challenges for next-generation intracortical brain-machine interfaces (iBMIs).
• Existing event-based frontends (EBFs) offer compression but are susceptible to false events, impacting neural decoding accuracy.
• Conventional spike detection methods face limitations with increasing buffer sizes, memory access power, and incompatibility with EBFs.

Purpose of the Study:

• To develop a novel event-based spike detection (Ev-SPD) algorithm compatible with compressive EBFs for high-density iBMIs.
• To design and implement a low-power in-memory computing (IMC) architecture for efficient event processing.
• To address the limitations of current spike detection techniques in high-channel-count neural implants.

Main Methods:

• Introduced an event-based spike detection (Ev-SPD) algorithm tailored for scalable compressive EBFs.
• Proposed a novel 10-transistor eDRAM-SRAM hybrid random-access memory (HRAM) in-memory computing (IMC) bitcell for event processing.
• Fabricated a 1024-channel IMC SPD macro and validated its performance using synthetic data and Neuropixel recordings.

Main Results:

• Achieved high spike detection accuracy: 96.06% on synthetic data and 95.08% similarity with Neuropixel recordings.
• Demonstrated ultra-low power consumption: 23.9 nW per channel.
• Achieved high area efficiency: 375 μm² per channel.

Conclusions:

• The developed Ev-SPD algorithm and IMC architecture offer a compatible solution for high-density iBMIs.
• The proposed system achieves significant reductions in power consumption and area while maintaining high accuracy.
• This work advances the development of scalable and efficient neural interfaces for brain-machine applications.