Hardware realization of memory-augmented neural networks using multi-level RRAM arrays

Area of Science:

• Materials Science
• Computer Science
• Electrical Engineering

Background:

• Conventional memory-augmented neural networks (MANNs) face data-movement bottlenecks.
• Efficient similarity-based retrieval is crucial for MANNs with limited data.

Purpose of the Study:

• To simulate a hardware-parameterized memory-augmented neural network (MANN) using multi-level RRAM crossbar arrays.
• To overcome data-movement bottlenecks in MANNs by performing computations directly in memory.

Main Methods:

• Simulated vector-matrix multiplication (VMM), locality-sensitive hashing (LSH), and content-addressable memory (CAM) within RRAM arrays.
• Achieved 5-bit multi-level cell (MLC) operation using an incremental step pulse with verification algorithm (ISPVA).
• Implemented a complete MANN pipeline with a CNN encoder, LSH, and differential 0T2R CAM.

Main Results:

• Demonstrated 4-bit precision in a 10 × 24 RRAM array with <1.8% accuracy loss for image classification.
• Showcased in-memory mapping of convolutional kernels (Sobel, Gaussian, Embossing) via analog VMM.
• Achieved 83.6% (5-way 1-shot) and 90.4% (5-shot) accuracy in hardware-aware MANN simulations.

Conclusions:

• In-memory MANNs using RRAM arrays offer a promising solution for low-power, scalable few-shot learning.
• Hardware-aware simulation validates the potential of RRAM-based MANNs to match software performance.
• Precise analog programmability in RRAM enables efficient on-chip learning and retrieval.