A ferroelectric-resistive dual-mode capacitor for unified KV-cache and weight storage toward Transformer acceleration

This study proposes processing-in-memory (PIM) architecture based on a dual-mode capacitor to address the memory bottleneck and power consumption issues arising from the rapid expansion of large language models (LLMs). In large-scale AI systems, the key-value cache (KV-cache) is essential for handling massive parameters; however, as the cache size increases proportionally with context length, DRAM usage and power consumption surge, leading to memory bottlenecks. To mitigate this, we introduce a PIM architecture that performs computations directly within memory, thereby reducing data transfer overhead. While the conventional analog PIM architecture enables fast and energy-efficient computation, it is unsuitable for dynamic attention operations in Transformer models and suffers from increased power consumption and reduced endurance due to frequent write operations in KV-cache processing. To overcome these limitations, the proposed dual-mode capacitor supports both ferroelectric tunnel junction (FTJ) and resistive random-access memory (RRAM) modes, enabling selective functionality depending on computational demands, providing low-power and high-speed operation in FTJ mode and high-reliability, multilevel data storage in RRAM mode. Experimental results confirmed that the HfZrO_x (HZO) device can be irreversibly converted from the FTJ mode to the RRAM mode through a forming process. Accordingly, individual cells within the same array architecture can be preconfigured in either the FTJ or RRAM mode according to their designated functions, thereby enabling the integrated implementation of KV-cache storage, weight storage, and multiply-and-accumulate (MAC) operation.