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Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model.

Omnia S Fadl1, Mohamed F Abu-Elyazeed1, Mohamed B Abdelhalim2

  • 1Electronics and Communications Department, Faculty of Engineering, Cairo University, University Street, P.O. Box 268, Giza 12316, Egypt.

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|February 5, 2016
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Summary

This study introduces a fast, deterministic method for estimating dynamic power consumption in CMOS circuits. The technique significantly reduces processing time compared to traditional simulation methods.

Keywords:
CMOS combinational logic circuitsDynamic power estimationLogic picturesReal-delay modelSwitching activityToggle rate

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Area of Science:

  • Electrical Engineering
  • Computer Engineering

Background:

  • Dynamic power estimation is crucial for VLSI circuit design.
  • Node toggle rate is a key parameter influencing circuit operation and power consumption.

Purpose of the Study:

  • To present a deterministic and rapid method for estimating dynamic power in CMOS combinational logic circuits.
  • To utilize the Logic Pictures concept for accurate toggle rate determination.

Main Methods:

  • Employing gate-level circuit descriptions.
  • Implementing a real-delay model for logic gates.
  • Leveraging the Logic Pictures concept to calculate node toggle rates.

Main Results:

  • The proposed method provides accurate dynamic power estimations.
  • Validation against exhaustive and Monte Carlo simulations confirms the technique's efficacy.
  • Achieved up to 96% reduction in processing time compared to exhaustive simulation.

Conclusions:

  • The developed method offers a significant speed-up for dynamic power estimation in VLSI design.
  • This approach enhances the efficiency of designing CMOS combinational logic circuits.