MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

Area of Science:

• Computer Engineering
• Electrical Engineering
• VLSI Design

Background:

• Input/Output (I/O) is a critical bottleneck for scaling down system size and power consumption.
• Current interconnects often suffer from high power draw and complex control mechanisms, hindering the development of ultra-low power systems.

Purpose of the Study:

• To introduce MBus, a novel chip-to-chip interconnect designed for ultra-low power systems.
• To demonstrate MBus's ability to enable invisible computing by addressing I/O limitations.

Main Methods:

• Developed MBus, a 4-pin interconnect utilizing two "shoot-through" rings.
• Implemented automatic power-gating for individual chips within the system.
• Introduced a "power oblivious communication" primitive.

Main Results:

• MBus achieves an energy efficiency of 22.6 pJ/bit/chip.
• Demonstrated seamless operation across FPGAs and custom chips from multiple semiconductor processes.
• A 2.2 mm³ three-chip system exhibited 8 nW total standby power.

Conclusions:

• MBus significantly reduces power consumption for chip-to-chip communication.
• The interconnect simplifies the creation of modular, heterogeneous systems operating at nanowatt levels.
• MBus offers a viable solution for achieving the goals of invisible computing.