A 99nW 70.4kHz Resistive Frequency Locking On-Chip Oscillator with 27.4ppm/°C Temperature Stability

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Microelectronic Systems

Background:

• Conventional relaxation oscillators often suffer from high power consumption and limited temperature stability due to the inclusion of comparators.
• System-on-chip (SoC) designs require highly efficient and stable on-chip timing references.

Purpose of the Study:

• To present a novel low-power on-chip oscillator suitable for system-on-chip (SoC) applications.
• To improve temperature stability and reduce power consumption compared to traditional oscillator designs.

Main Methods:

• Introduction of a resistive frequency locking loop topology.
• Matching the equivalent resistance of a switched-capacitor to a temperature-compensated resistor.
• Elimination of the traditional comparator from the oscillation loop.

Main Results:

• Fabricated in 0.18μm CMOS technology.
• Achieved a temperature stability of 27.4ppm/°C.
• Demonstrated long-term stability of less than 7ppm.
• Consumed only 99.4nW of power at an operating frequency of 70.4 kHz.

Conclusions:

• The proposed oscillator topology effectively eliminates the power-hungry comparator, leading to significant power savings.
• The resistive frequency locking loop ensures excellent temperature and long-term stability, crucial for SoC designs.
• This design offers a promising solution for low-power, high-stability timing references in integrated circuits.