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Updated: Mar 23, 2026

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Published on: July 24, 2015
High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures
Yuan Liu1, Jiming Sheng1, Hao Wu1
1Department of Materials Science and Engineering, University of California, Los Angeles, CA, 90095, USA.
Abstract:
Scalable fabrication of vertical-tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm(-2) . This study demonstrates that the interfacial native oxide plays a crucial role in governing the carrier transport in graphene-silicon heterostructures.
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