Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

Area of Science:

• Optoelectronics
• Integrated Circuits
• Photonics

Background:

• Optoelectronic receivers are crucial components in optical communication systems.
• Existing receivers often face challenges with power consumption and sensitivity.
• Monolithic integration offers a path to improved performance and reduced form factor.

Purpose of the Study:

• To develop a monolithically integrated optoelectronic receiver with a low-capacitance on-chip photodiode.
• To achieve high sensitivity and energy efficiency at high data rates.
• To demonstrate the viability of an opto-CMOS process for advanced receiver design.

Main Methods:

• Fabrication of the receiver using a 0.35 μm opto-CMOS process.
• Integration of a low-capacitance p-i-n photodiode directly onto the chip.
• Utilization of a regenerative latch as a sense amplifier for low power consumption.

Main Results:

• The integrated receiver operates at microwatts (μW) power levels.
• Achieved sensitivities of -26.0 dBm (635 nm) and -25.5 dBm (675 nm) at 400 Mbit/s (BER = 10⁻⁹).
• Demonstrated exceptional energy efficiency of 2 pJ/bit.

Conclusions:

• The developed optoelectronic receiver offers a significant advancement in performance and energy efficiency.
• Monolithic integration in an opto-CMOS process is effective for creating high-performance receivers.
• This technology holds promise for next-generation optical communication systems requiring low power and high speed.