Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications

Area of Science:

• Quantum computing
• Integrated photonics
• Semiconductor device physics

Background:

• Photonic quantum simulators require precise control over photon detection.
• Integrated single-photon avalanche diodes (SPADs) are key components for sensitive light detection.
• Existing gating circuits may lack the speed and integration necessary for advanced quantum applications.

Purpose of the Study:

• To introduce and characterize a novel monolithic gating circuit for photonic quantum simulators.
• To evaluate the performance of integrated SPADs within the developed gating circuit.
• To demonstrate the potential of the circuit for high-fidelity quantum information processing.

Main Methods:

• Monolithic implementation of a nine-channel gating circuit using 0.18 µm high-voltage CMOS technology.
• Integration of nine SPADs within an application-specific integrated circuit (ASIC).
• Characterization of circuit parameters including rise/fall times, pulse width, detection threshold, and power consumption.

Main Results:

• Achieved fast rise and fall times of 480 ps and 280 ps, with a minimum pulse width of 1.26 ns.
• Enabled a low detection threshold for avalanche events (<100 mV) using a fast comparator.
• Demonstrated a photon detection probability of ~50% at 9.9 V excess bias and 635 nm wavelength.
• Total power consumption for nine channels is approximately 250 mW.

Conclusions:

• The developed gating circuit offers high performance metrics suitable for photonic quantum simulation.
• The integrated SPADs exhibit promising characteristics for quantum applications.
• This ASIC-based solution advances the development of compact and efficient quantum computing hardware.