Modularized architecture of address generation units suitable for real-time processing MR data on an FPGA

Area of Science:

• Computer Engineering
• Digital Systems Design
• Algorithm Implementation

Background:

• Address Generation Units (AGUs) are crucial for data processing, especially in complex algorithms like Fast Fourier Transforms (FFTs).
• Existing AGU designs can be rigid, limiting their adaptability to diverse data structures and applications.
• Field Programmable Gate Arrays (FPGAs) offer a flexible platform for hardware acceleration, but efficient AGU design is key.

Purpose of the Study:

• To present a novel modular approach for designing Address Generation Units (AGUs).
• To demonstrate the application of this modular design for 2D and 3D Fast Fourier Transform (FFT) algorithms on Field Programmable Gate Arrays (FPGAs).
• To explore the potential of the proposed AGUs for handling irregularly structured data, such as that from magnetic resonance imaging.

Main Methods:

• Development of a generic Address Generation Core (AGC) as a fundamental building block.
• Construction of AGUs by assembling multiple AGCs for modularity and expandability.
• Implementation and testing of AGUs for 2D and 3D FFT on an FPGA platform.

Main Results:

• The developed AGUs are simple, easily expandable, and capable of handling 2D and 3D structured data.
• Experimental results confirm automatic address generation with user-defined patterns at one address per clock cycle.
• The AGUs operate at clock rates up to 80 MHz and can run concurrently with other processes without adding latency.

Conclusions:

• The modular AGU design approach offers significant advantages in simplicity, expandability, and performance.
• The proposed AGUs are effective for accelerating 2D and 3D FFT algorithms on FPGAs.
• The modular design methodology is expected to have broad applicability beyond FFTs, including support for irregularly structured data in fields like medical imaging.