Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems

Area of Science:

• Neuromorphic Engineering
• Computer Architecture
• Computational Neuroscience

Background:

• Neuromorphic systems require efficient communication protocols for large-scale neural and synaptic event transmission.
• Existing address-event representation protocols face scalability challenges in multichip and multiboard configurations.

Purpose of the Study:

• To introduce a hierarchical address-event routing (HiAER) architecture for scalable neuromorphic communication.
• To enable biologically plausible neural network simulations with programmable synaptic parameters.

Main Methods:

• Implementation using Xilinx Spartan-6 FPGAs and custom analog neuromorphic ICs.
• Extension of the address-event representation protocol to a multi-level hierarchical bus structure.
• Integration of individually programmable axonal delay and synaptic strength.

Main Results:

• The HiAER architecture supports 262,000 neurons and 262 million synapses.
• Demonstrated approximately linear scaling of synaptic event throughput with network size.
• Achieved a throughput of 3.6 x 10^7 synaptic events per second per 16k-neuron node.

Conclusions:

• The HiAER architecture provides a scalable solution for inter-processor communication in large-scale neuromorphic systems.
• The protocol's features support the development of more biologically realistic neural network models.
• The system is suitable for reconfigurable, large-scale neuromorphic computing applications.