DRAM Weak Cell Characterization for Retention Time.

Area of Science:

• Semiconductor Device Physics
• Memory Technology
• Integrated Circuit Reliability

Background:

• Data retention is critical for Dynamic Random-Access Memory (DRAM) performance and reliability.
• Identifying weak cells is essential for improving DRAM yield and preventing data loss.
• Existing methods may lack the precision to diagnose root causes of retention failures.

Purpose of the Study:

• To propose and validate a novel testing sequence for detecting refresh weak cells in DRAM.
• To differentiate retention failure mechanisms based on root causes.
• To enable precise Physical Failure Analysis (PFA) by locating failure origins.

Main Methods:

• Developing a test sequence analyzing data retention time distribution under varied bias conditions.
• Categorizing retention failures into Gate Induced Drain Leakage (GIDL), sub-threshold leakage, and junction leakage.
• Analyzing 30 nm design-rule DRAM cells featuring Recess Channel Array Transistor (RCAT) and Buried Channel Array Transistor (BCAT).

Main Results:

• The proposed method successfully detected and categorized weak cells in 30 nm DRAM.
• Most weak cells were identified as GIDL leaky cells in both BCAT and RCAT technologies.
• For BCAT, process-induced variations in word line to storage node distance were the primary cause of weak cells.
• For RCAT, sharp corners in the active layer of the storage node were identified as the main origin of weak cells.

Conclusions:

• The proposed testing sequence is feasible for characterizing data retention weak cells.
• Failure categorization aids in understanding and mitigating specific physical failure mechanisms in DRAM.
• Device structure (BCAT vs. RCAT) significantly influences the dominant root causes of weak cells.