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Metal-Free CVD Graphene Synthesis on 200 mm Ge/Si(001) Substrates.

M Lukosius1, J Dabrowski1, J Kitzmann1

  • 1IHP , Im Technologiepark 25, 15236 Frankfurt (Oder), Germany.

ACS Applied Materials & Interfaces
|December 15, 2016
PubMed
Summary

High-quality, defect-free graphene was successfully synthesized on 200 mm germanium-on-silicon wafers using chemical vapor deposition. This advancement is compatible with complementary-metal-oxide-semiconductor technology, paving the way for new electronic applications.

Keywords:
200 mmCMOSCVDGe(001)ab initio DFTfacetinggraphene synthesisnucleation

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Area of Science:

  • Materials Science
  • Nanotechnology
  • Solid State Physics

Background:

  • Graphene synthesis on silicon-based substrates is crucial for integrating advanced electronic materials.
  • Germanium-on-silicon (Ge/Si) wafers offer a promising platform for high-quality graphene growth.
  • Controlling defects and ensuring wafer-scale uniformity are key challenges in graphene production.

Purpose of the Study:

  • To synthesize high-quality, complementary-metal-oxide-semiconductor (CMOS) technology-compatible graphene on 200 mm Ge/Si wafers.
  • To characterize the structural and electrical properties of the synthesized graphene.
  • To elucidate the underlying mechanisms governing graphene growth on Ge(001).

Main Methods:

  • Chemical vapor deposition (CVD) using methane on epitaxial Ge(100) layers grown on Si(100) at 885 °C.
  • Raman spectroscopy for structural quality assessment (2D/G ratio, D mode, 2D peak FWHM).
  • Electrical characterization (sheet resistance, mobility) after transferring graphene to SiO2/Si substrates.
  • Density Functional Theory (DFT) calculations to understand growth mechanisms.

Main Results:

  • Wafer-scale synthesis of high-quality graphene (2D/G ratio ~3, low D mode) on 200 mm Ge/Si wafers.
  • Graphene exhibited good structural quality with a 2D peak FWHM of 39 cm⁻¹.
  • Transferred graphene showed promising electrical properties: sheet resistance ~1500 Ω/sq and mobility ~400 cm²/V s.
  • Lack of interfacial oxide correlated with superior graphene properties.
  • DFT calculations explained hydrogen-induced nucleation reduction, graphene-induced facet formation, and domain orientation.

Conclusions:

  • Successful synthesis of CMOS-compatible, high-quality graphene on 200 mm Ge/Si wafers via CVD.
  • The study provides insights into growth mechanisms, attributing high quality to specific surface interactions and lattice matching.
  • The results demonstrate the potential of Ge/Si substrates for scalable, high-performance graphene integration in electronics.