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A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

Hilal Tayara1, Woonchul Ham2, Kil To Chong3

  • 1Department of Electronics and Information Engineering, Chonbuk National University, Jeonju 54896, Korea. hilaltayara@jbnu.ac.kr.

Sensors (Basel, Switzerland)
|December 17, 2016
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This study presents a novel real-time visual sensor architecture for mobile robot localization and navigation. The system achieves high performance using hardware acceleration on an FPGA and a System on Chip (SoC) for efficient marker detection and pose calculation.

Area of Science:

  • Robotics and Computer Vision
  • Embedded Systems Engineering

Background:

  • Mobile robot localization and navigation are critical for autonomous systems.
  • Real-time processing of visual data is essential for accurate and responsive robot operation.
  • Existing methods often face challenges with computational complexity and latency.

Purpose of the Study:

  • To introduce a real-time marker-based visual sensor architecture for mobile robot localization and navigation.
  • To implement a hardware acceleration architecture for efficient post-video processing.
  • To achieve on-the-fly processing of pixel streams without frame buffering.

Main Methods:

  • Utilized a Field-Programmable Gate Array (FPGA) for hardware acceleration of the post-video processing system.
  • Implemented the pose calculation algorithm on a System on Chip (SoC) with an Altera Nios II soft-core processor.
Keywords:
FAST corner detectionFPGAcoplanar PosItimage segmentationvisual sensors

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  • Employed single-pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection for marker extraction.
  • Applied the Coplanar PosIT algorithm with floating-point hardware acceleration.
  • Used Taylor series and Lagrange polynomials for trigonometric function approximation and inverse square root method for square root computations.

    • Main Results:

    • Achieved real-time performance for marker-based visual sensor processing.
    • Demonstrated efficient extraction of predefined markers using FAST corner detection on FPGA.
    • Successfully implemented the Coplanar PosIT algorithm on the Nios II processor for accurate pose calculation.
    • Processed pixel streams on the fly, eliminating the need for input frame buffering.

    Conclusions:

    • The developed architecture enables real-time mobile robot localization and navigation.
    • Hardware acceleration on FPGA and SoC significantly improves processing speed and efficiency.
    • The system provides a robust solution for on-the-fly visual data processing in robotic applications.