Pseudo Asynchronous Level Crossing adc for ecg Signal Acquisition.

Area of Science:

• Electrical Engineering
• Biomedical Engineering
• Microelectronics

Background:

• Existing asynchronous level crossing ADCs often require digital-to-analog converters (DACs) and continuous-time comparators, increasing complexity and power usage.
• Implantable biomedical sensors demand ultra-low power consumption and minimal chip area for long-term operation.
• Robust performance in noisy environments is critical for reliable biomedical data acquisition.

Purpose of the Study:

• To introduce a new pseudo asynchronous level crossing ADC architecture optimized for low-power, implantable biomedical sensing.
• To eliminate the need for DACs and continuous-time comparators in asynchronous ADC designs.
• To enhance energy efficiency, reduce chip area, and improve noise immunity.

Main Methods:

• Developed a novel ADC architecture utilizing an analog memory cell and dynamic comparators.
• Implemented a signal activity-dependent sampling mechanism that triggers events only when the input signal changes.
• Fabricated the ADC using 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology.

Main Results:

• Achieved ultra-low power consumption of 0.6 µW.
• Occupied a small chip area of 0.0372 mm².
• Demonstrated robust performance with dynamic comparators, simplifying interfacing with synchronous processing blocks and achieving an equivalent number of bits (ENOB) up to 8 bits.

Conclusions:

• The proposed pseudo asynchronous level crossing ADC architecture offers significant advantages for low-power biomedical applications.
• The design's energy efficiency, small footprint, and noise robustness make it suitable for implantable sensors.
• Eliminating DACs and continuous-time comparators simplifies the design and enhances its overall performance and applicability.