A low-cost DAC BIST structure using a resistor loop.

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Testing and Verification

Background:

• Conventional digital-to-analog converter built-in self-test (DAC BIST) structures face challenges with area overhead and accuracy due to switch effects.
• Deterministic dynamic element matching analog-to-digital converters (DDEM ADC) are complex and contribute to these challenges.

Purpose of the Study:

• To propose a new DAC BIST structure that addresses the limitations of conventional methods.
• To reduce the area overhead and enhance the accuracy of DAC BIST through innovative techniques.

Main Methods:

• A novel resistor loop structure is employed, modifying resistor lengths via a merging operation.
• Techniques for switch reduction and switch effect mitigation are implemented.
• The proposed methods reduce the number of switches and resistors in the DAC BIST.

Main Results:

• The proposed DAC BIST structure significantly reduces resource utilization.
• The switch effect reduction method effectively mitigates mismatch errors caused by switches.
• Experimental results validate the improved accuracy and reduced resource usage.

Conclusions:

• The novel DAC BIST structure offers a viable solution for improving testing efficiency and accuracy in integrated circuits.
• The proposed switch reduction and mitigation techniques are effective in overcoming conventional limitations.
• This approach contributes to more efficient and reliable analog-to-digital converter testing.