HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition.

Area of Science:

• Neuromorphic Engineering
• Machine Learning
• Computer Architecture

Background:

• Hierarchical Temporal Memory (HTM) is an online machine learning algorithm inspired by the neocortex.
• Developing scalable on-chip HTM architectures remains a significant research challenge.
• The spatial pooler and temporal memory are key HTM substructures.

Purpose of the Study:

• To propose a novel Spatial Pooler circuit design for scalable on-chip HTM.
• To utilize parallel memristive crossbar arrays for 2D columns within the Spatial Pooler.
• To validate the proposed circuit's performance on benchmark datasets.

Main Methods:

• A new Spatial Pooler circuit design employing parallel memristive crossbar arrays was developed.
• Circuit simulations were conducted using a practical memristor device model and 0.18 μm IBM CMOS technology.
• Performance was evaluated on face recognition (AR, YALE, ORL, UFI datasets) and speech recognition (TIMIT dataset).

Main Results:

• The proposed Spatial Pooler circuit design demonstrated effective performance in both face and speech recognition tasks.
• Simulation results validated the feasibility and efficiency of the memristive crossbar-based design.
• The design integrates HTM's core components for potential on-chip implementation.

Conclusions:

• The novel Spatial Pooler circuit design offers a promising approach for scalable on-chip HTM architectures.
• Memristive crossbar arrays are suitable for implementing HTM's spatial pooling function efficiently.
• This work contributes to advancing neuromorphic computing hardware for intelligent systems.