Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes

Area of Science:

• Semiconductor physics
• Materials science
• Nanoelectronics

Background:

• Two-dimensional (2D) materials are promising for next-generation field-effect transistors (FETs).
• Existing assessments lack comprehensive analysis of 2D FETs for high-performance logic using system-level metrics like delay and energy-delay product.

Purpose of the Study:

• To establish guidelines for 2D material-based FETs to meet sub-10nm high-performance logic requirements.
• To focus on material properties, device design, and energy-delay optimization.
• To explore the feasibility of 2D FETs in advanced technology nodes.

Main Methods:

• Analysis of material requirements, including effective mass and anisotropicity.
• Proposal of novel device designs using monolayer black phosphorus.
• Simulation and assessment of device performance at sub-5nm gate lengths.

Main Results:

• 2D materials require smaller effective mass and anisotropicity for future high-performance logic.
• Novel device designs using monolayer black phosphorus are proposed for sub-5nm gate lengths.
• 2D electrostatics, not tunneling, become the primary challenge below 5nm gate lengths.

Conclusions:

• Meeting sub-5nm gate length delay and energy-delay targets necessitates scaling both supply voltage (V_DD) and effective-oxide-thickness (EOT) below 0.5V and 0.5nm, respectively.
• Further research into gate stack design and material properties is crucial for advancing 2D FET technology.