Monolithically-Integrated TE-mode 1D Silicon-on-Insulator Isolators using Seedlayer-Free Garnet.

Area of Science:

• Photonics
• Materials Science
• Electrical Engineering

Background:

• Integrated photonic circuits require efficient isolators for signal integrity.
• Existing silicon-on-insulator (SOI) isolators often rely on TM-modes, necessitating complex polarization control for TE-mode sources.
• There is a need for compact, scalable isolators compatible with on-chip TE-mode operation.

Purpose of the Study:

• To experimentally demonstrate the first TE-mode silicon-on-insulator (SOI) isolators utilizing Faraday Rotation (FR).
• To address the limitations of existing nonreciprocal phase shift (NRPS) isolators for TE-mode photonic circuits.
• To develop a fabrication method for scalable and efficient on-chip optical isolators.

Main Methods:

• Fabrication of 1D 2-element waveguide isolators using lithography and sputter deposition.
• Integration of garnet claddings and application of longitudinal magnetic fields to induce nonreciprocal mode conversion (waveguide equivalent of FR).
• Utilizing quasi-phase matched claddings to mitigate birefringence limitations.

Main Results:

• Achieved isolation ratios of 11 dB and insertion losses of 4 dB in the experimental TE-mode SOI isolators.
• Demonstrated a fabrication process amenable to facile upscaling compared to alternative methods.
• Identified pathways for future designs to achieve isolation ratios exceeding 30 dB with losses below 6 dB.

Conclusions:

• The developed Faraday Rotation (FR) SOI isolators represent a significant advancement for source-integrated near-infrared photonic circuits.
• These isolators overcome the TM-mode dependency of previous NRPS devices, simplifying integration with standard TE-mode lasers.
• The lithography and sputter deposition fabrication offers a scalable solution for on-chip optical isolation.