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Hardware-Efficient On-line Learning through Pipelined Truncated-Error Backpropagation in Binary-State Networks.

Hesham Mostafa¹, Bruno Pedroni², Sadique Sheik³

¹Institute for Neural Computation, University of California, San DiegoSan Diego, CA, United States.

Frontiers in Neuroscience

|September 22, 2017

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This study introduces a hardware-efficient method for accelerating artificial neural network (ANN) training using pipelined backpropagation. This on-line learning technique reduces computation and memory needs, making deep network training more practical.

Area of Science:

Computer Science
Machine Learning
Hardware Acceleration

Background:

Artificial neural networks (ANNs) excel in benchmarks, with focus on accelerating inference.
Accelerating the training phase of ANNs has received less attention.
Custom silicon devices exist for ANN inference acceleration.

Purpose of the Study:

To present a hardware-efficient on-line learning technique for feedforward multi-layer ANNs.
To accelerate the training phase of ANNs by integrating learning with inference.
To reduce computational and memory requirements for ANN training.

Main Methods:

Pipelined backpropagation for on-line learning, performing learning in parallel with the forward pass.
Utilizing binary state variables in the feedforward network and ternary errors in truncated-error backpropagation.

Keywords:

binary neural networks hardware accelerators online learning pipelined backpropagation supervised learning

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Eliminating multiplications and reducing memory needs for efficient hardware implementation.

Main Results:

Demonstrated on-line learning of MNIST handwritten digit classification on an FPGA.
Achieved small degradation in test error performance compared to off-line trained binary ANNs.
Showcased reduced computation and memory requirements through synergy of pipelined backpropagation and binary-state networks.

Conclusions:

Pipelined on-line learning is practical for deep networks.
The proposed technique offers significant reductions in computation and memory.
This approach enables efficient hardware implementation of ANN training.