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    Advanced mask synthesis using a vector imaging model improves pattern fidelity for semiconductor manufacturing. This new method addresses limitations of scalar models in critical dimension reduction for 22nm nodes and beyond.

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    Area of Science:

    • * Optical lithography and semiconductor manufacturing.
    • * Computational electromagnetics and imaging science.

    Background:

    • * Critical dimension (CD) shrinking in semiconductor manufacturing necessitates advanced lithography techniques.
    • * Scalar imaging models are insufficient for 22nm technology nodes and beyond due to the vector nature of electromagnetic fields.
    • * Immersion lithography systems require more sophisticated mask synthesis approaches.

    Purpose of the Study:

    • * To develop an optimized mask synthesis framework using a vector imaging model.
    • * To address the limitations of scalar imaging models in advanced semiconductor lithography.
    • * To improve pattern fidelity and reduce edge placement error in photomask synthesis.

    Main Methods:

    • * Establishment of a forward model for vector image formation.
    • * Formulation of photomask synthesis as an inverse imaging problem.
    • * Application of a level-set based optimization framework with a stable time-dependent model.
    • * Solution using conjugate gradient methods and finite-difference schemes.

    Main Results:

    • * Demonstrated pronounced improvements in pattern fidelity.
    • * Significant reduction in edge placement error.
    • * Achieved notable computation acceleration and enhanced convergence performance.
    • * Validated the effectiveness of the vector imaging model for mask synthesis.

    Conclusions:

    • * The developed level-set based vector imaging model offers superior performance for photomask synthesis compared to scalar models.
    • * The framework provides a robust and efficient solution for advanced semiconductor lithography challenges.
    • * The approach enables higher accuracy and faster computation for critical dimension control in next-generation integrated circuits.