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Thickness Dependent Parasitic Channel Formation at AlN/Si Interfaces
Hareesh Chandrasekar1,2,3, K N Bhat4, Muralidharan Rangarajan4
1Centre for Nano Science and Engineering, Indian Institute of Science, Bangalore, 560012, India. hareeshc2408@gmail.com.
Scientific Reports
|November 18, 2017
Summary
The parasitic conduction channel in Gallium Nitride-on-Silicon (GaN-on-Silicon) devices is linked to silicon surface acceptors, primarily Si-O-N complexes. This finding helps improve GaN-on-Silicon device performance.
Area of Science:
- Materials Science
- Semiconductor Physics
- Device Engineering
Background:
- Gallium Nitride-on-Silicon (GaN-on-Silicon) electronic devices suffer performance degradation due to parasitic conduction pathways at the nitride-substrate interface.
- These parasitic channels cause increased switching losses and reduced breakdown voltages, hindering device efficiency.
Purpose of the Study:
- To investigate the physical nature and properties of the parasitic conduction channel at Aluminum Nitride/Silicon (AlN/Si) interfaces.
- To understand the thickness dependence of parasitic channel formation and its underlying mechanisms.
Main Methods:
- Secondary Ion Mass Spectroscopy (SIMS) was employed to analyze the origin of surface acceptor densities at the AlN/Si interface.
- Low-temperature (5 Kelvin) magneto-resistance (MR) measurements were conducted to probe the electronic properties of the interface.
Main Results:
- A strong thickness dependence of parasitic channel formation was observed, linked to increased surface acceptor densities in silicon.
- SIMS analysis identified Si-O-N complexes as the source of thermal acceptor formation.
- Magneto-resistance data indicated the presence of an electron inversion layer, contributing to parasitic conduction, though secondary at room temperature.
Conclusions:
- The study elucidates the critical role of silicon surface acceptors, specifically Si-O-N complexes, in forming parasitic channels at AlN/Si interfaces.
- Understanding these mechanisms is crucial for mitigating performance issues in GaN-on-Silicon electronic devices and optimizing their design.

