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Area of Science:

  • Computer Architecture
  • Energy Efficiency
  • High Performance Computing (HPC)

Background:

  • Unsustainable energy consumption necessitates evaluating architecture designs for energy efficiency in HPC and datacenters.
  • Existing power measurement methods (external meters, power models) have accuracy and adoption drawbacks.
  • Intel Running Average Power Limit (RAPL) offers improved accuracy and time resolution for power measurement.

Purpose of the Study:

  • To conduct an in-depth evaluation of architecture designs' impact on system energy efficiency.
  • To leverage RAPL for fine-grained energy tracking at subcomponent levels (CPU cores, uncore, DRAM).
  • To analyze the effects of Non-Uniform Memory Access (NUMA), Simultaneous Multithreading (SMT), and Turbo Boost on energy efficiency.

Main Methods:

  • Utilized representative serial and parallel benchmark suites.
  • Employed Intel Running Average Power Limit (RAPL) for subcomponent-level energy tracking.
  • Evaluated architectural features: Non-Uniform Memory Access (NUMA), Simultaneous Multithreading (SMT), and Turbo Boost.

Main Results:

  • NUMA effect causes power/energy surges and significantly degrades energy efficiency due to compute-memory mismatch.
  • SMT enhances energy efficiency for most multithreaded applications (e.g., PARSEC) by over 40% reduction in average power.
  • Turbo Boost accelerates execution and saves energy but may be unsuitable for power-constrained systems.

Conclusions:

  • NUMA architecture significantly impacts HPC energy efficiency negatively.
  • SMT presents a viable strategy for improving energy efficiency in HPC workloads.
  • Turbo Boost offers performance and energy benefits but requires careful consideration within power budgets.