A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

Area of Science:

• Electrical Engineering
• Semiconductor Manufacturing
• Materials Science

Background:

• Three-dimensional integration circuits (3DICs) offer enhanced performance and miniaturization.
• Stacking misalignment is a critical challenge impacting 3DIC yield and reliability.
• Current inspection methods for stacking faults can be inefficient or complex.

Purpose of the Study:

• To propose a novel electrical measurement method for inspecting stacking misalignment in 3DICs.
• To develop a test structure capable of detecting the direction and quantity of stacking faults.
• To enhance the efficiency of 3DIC inspection processes.

Main Methods:

• Design of a specialized metal line pattern for electrical detection.
• Integration of the pattern with a bump-less Through-Silicon Via (TSV) fabrication process.
• Utilizing the current mirror concept for circuit simulation and measurement.

Main Results:

• Successful detection of stacking fault direction and quantity using the proposed method.
• Demonstration of the effectiveness of the metal line pattern and bump-less TSV process.
• Achieved improved measurement efficiency through circuit simulation.

Conclusions:

• The proposed electrical measurement method provides an efficient and accurate solution for inspecting stacking misalignment in 3DICs.
• The developed test structure and fabrication process are viable for detecting stacking faults.
• This technique contributes to enhancing the reliability and yield of 3D integrated circuits.