Effects of the Grain Boundary and Interface Traps on the Electrical Characteristics of 3D NAND Flash Memory Devices

Three-dimensional (3D) NAND flash memory devices having a poly-silicon channel with grain boundaries, the cylindrical macaroni channel being outside the inter-oxide filler layer and inside the tunneling oxide layer, were evaluated. The effects of the grain size, grain boundary trap density, and interface trap density at the interfaces between the channel and the oxide layers on the electrical characteristics of 3D NAND flash memory devices were investigated. The electron density of the channel was changed depending on the grain boundary trap density and the position of the grain boundary trap in the channel. The grain boundary traps increased the potential barrier and decreased the electron density of the channel. The threshold voltage increased with increasing grain boundary trap density and interface trap density.