Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Manufacturing

Background:

• Wafer warpage is a critical challenge in advanced packaging, impacting process integration and device reliability.
• Fan-out wafer-level packaging (FO-WLP) offers a TSV-less interconnection solution, requiring precise warpage control.
• Novel redistribution layer (RDL)-first approaches aim to improve packaging performance and manufacturability.

Purpose of the Study:

• To investigate TSV-less interconnection using FO-WLP with an RDL-first approach.
• To evaluate and optimize wafer warpage through finite element analysis (FEA) for a 12-inch wafer.
• To validate simulation results with experimental measurements and assess interconnection quality.

Main Methods:

• Finite Element Analysis (FEA) to simulate warpage under varying geometric and material parameters.
• Experimental validation using an optical surface inspector to measure wafer profile.
• Electrical measurements to evaluate the quality of the TSV-less interconnection structure.
• Investigation of glass carriers with different coefficients of thermal expansion (CTE).

Main Results:

• FEA successfully predicted wafer warpage, identifying key parameters influencing the phenomenon.
• Experimental measurements correlated well with FEA simulations, confirming the predictive accuracy.
• Electrical testing demonstrated the viability and quality of the novel TSV-less interconnection using the RDL-first FO-WLP process.

Conclusions:

• The RDL-first FO-WLP technology provides a viable path for TSV-less interconnections.
• FEA is an effective tool for optimizing warpage in large-diameter wafers for advanced packaging.
• Careful consideration of geometric dimensions, material properties, and carrier selection is crucial for mitigating warpage issues.