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The important convolution properties include width, area, differentiation, and integration properties.
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A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems

Luis A Camuñas-Mesa1, Yaisel L Domínguez-Cordero1, Alejandro Linares-Barranco2

  • 1Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC y Universidad de Sevilla, Sevilla, Spain.

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Summary
This summary is machine-generated.

This study introduces a flexible hardware implementation for Convolutional Neural Networks (ConvNets) on FPGAs, enabling efficient real-time processing of high-speed visual data. The novel event-driven node achieves high recognition rates with low power consumption.

Keywords:
Address Event Representation (AER)Reconfigurable Networksconvolutional neural networksevent-driven processingneural network hardwareneuromorphic vision

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Neuroscience-inspired Computing

Background:

  • Traditional software-based Convolutional Neural Networks (ConvNets) face scalability challenges and limitations in real-time processing.
  • Existing hardware implementations of ConvNets lack the flexibility required for diverse applications.

Purpose of the Study:

  • To propose a fully configurable, event-driven convolutional node for implementing arbitrary ConvNets on FPGAs.
  • To introduce a rate saturation mechanism that emulates biological neuron refractory behavior for event-driven processing.

Main Methods:

  • Developed a configurable event-driven convolutional node with a processing unit and routing element for FPGA implementation.
  • Integrated a rate saturation mechanism to ensure temporal separation of events, mimicking biological neurons.
  • Implemented a 4-layer ConvNet for poker card recognition on a Spartan6 FPGA, tested with Dynamic Vision Sensor (DVS) data.

Main Results:

  • Achieved a 96% recognition rate with 0.85 mW power consumption for slow stimulus playback.
  • Demonstrated robustness at maximum playback speed, achieving over 63% recognition with downsampling of input events.
  • Validated the system's capability for high-speed processing and real-time applications.

Conclusions:

  • The proposed FPGA-based event-driven convolutional node offers a flexible and efficient solution for implementing complex ConvNets.
  • The rate saturation mechanism enhances the system's ability to handle high-speed, event-based data streams.
  • This approach paves the way for real-time, low-power AI applications in areas like robotics and autonomous systems.