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Related Experiment Video

Updated: Feb 13, 2026

The Participant-Reported Implementation Update and Score PRIUS: A Novel Method for Capturing Implementation-Related Data Over Time

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A shared synapse architecture for efficient FPGA implementation of autoencoders.

Akihiro Suzuki¹, Takashi Morie¹, Hakaru Tamukoh¹

¹Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology, 2-4 Hibikino, Wakamatsu-ku, Kitakyushu 808-0196, Japan.

|March 16, 2018

Summary

This summary is machine-generated.

This study introduces a shared synapse architecture for autoencoders (AEs), optimizing FPGA resource usage. The novel design effectively halves synapse modules, enabling efficient implementation of single and stacked AEs.

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Area of Science:

Digital circuits
Computer engineering
Artificial intelligence

Background:

Autoencoders (AEs) are neural networks used for unsupervised learning.
Field-programmable gate arrays (FPGAs) offer hardware acceleration for complex computations.
Efficient resource utilization in FPGA implementations of AEs is crucial for practical applications.

Purpose of the Study:

To propose and implement a novel shared synapse architecture for autoencoders on FPGAs.
To reduce resource consumption and module count in FPGA-based AE circuits.
To demonstrate the adaptability and performance of the proposed architecture for various AE configurations.

Main Methods:

Design and logical synthesis of a shared synapse architecture for AEs.
Implementation of the architecture as a digital circuit on an FPGA.
Parameterization of the circuit to adjust layer units, bit width, and learning rate for flexibility.
Formulation of clock cycle equations for theoretical performance estimation.

Main Results:

The shared synapse architecture significantly reduces FPGA resource utilization compared to non-shared designs.
The number of synapse modules is halved, leading to more efficient hardware implementation.
Implemented single and stacked AE circuits with the proposed architecture function correctly.
Scalability and the impact of bit width on learning performance were analyzed.

Conclusions:

The proposed shared synapse architecture offers an efficient method for implementing autoencoders on FPGAs.
The architecture supports the construction of both single and stacked autoencoders with reduced hardware overhead.
The developed clock cycle formulation allows for accurate performance prediction in diverse network configurations.