Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers.

Area of Science:

• Electrical Engineering
• Microelectronics
• Energy Harvesting

Background:

• Low-power applications like wireless sensing nodes (WSNs) require efficient voltage multipliers.
• Energy harvesting sources often provide intermittent or low-level AC input signals.
• Existing voltage multipliers face challenges in efficiency and chip area for these applications.

Purpose of the Study:

• To present a novel threshold-compensation technique for multi-stage voltage multipliers.
• To enable a topological design methodology for maximizing voltage conversion efficiency (VCE).
• To reduce physical chip area occupation for a given output performance.

Main Methods:

• Developed a threshold-reduction technique for voltage multipliers.
• Employed an optimal control of transistor conductivity and leakage losses.
• Utilized simulation and experimental validation with 2N5247 N-channel junction field effect transistors (JFETs).

Main Results:

• Simulations confirmed the validity of the proposed design methodology.
• Experimental results demonstrated the effectiveness of the threshold-reduction approach.
• The technique significantly reduces chip area for target output performance.

Conclusions:

• The proposed threshold-compensation technique enhances VCE in low-power voltage multipliers.
• This approach offers a significant reduction in chip area for WSNs and similar applications.
• The methodology provides a valuable design space for optimizing voltage multiplier performance.