Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor

Area of Science:

• Semiconductor device physics
• Advanced electronic materials

Background:

• Traditional dynamic random-access memory (DRAM) architectures face scaling challenges.
• Junctionless transistors offer a promising alternative for future memory technologies.

Purpose of the Study:

• To propose and simulate a novel one-transistor dynamic random-access memory (1T-DRAM) device.
• To investigate the impact of dual gate workfunctions on memory performance.
• To optimize device parameters for enhanced sensing margin and data retention.

Main Methods:

• Technology computer-aided design (TCAD) simulations were employed.
• A symmetric double-gate silicon junctionless transistor architecture was designed.
• Device operation was analyzed across four states: write '1', write '0', read, and hold.
• The influence of varying gate workfunctions on performance metrics was systematically studied.

Main Results:

• The proposed 1T-DRAM device demonstrated effective hole storage by adjusting potential barriers via dual gate workfunctions.
• Optimized gate workfunctions yielded a sensing margin of 33 μA/μm.
• An impressive retention time of 38 ms was achieved with the optimized device configuration.

Conclusions:

• The symmetric double-gate Si junctionless transistor is a viable architecture for 1T-DRAM applications.
• Dual gate workfunction engineering is crucial for optimizing sensing margin and retention characteristics.
• The proposed device shows potential for high-performance and reliable non-volatile memory solutions.