Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs

Atsushi Nose1, Tomohiro Yamazaki2, Hironobu Katayama3

  • 1Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan. Atsushi.Nose@sony.com.

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