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Electrically-triggered micro-explosion in a graphene/SiO2/Si structure
Siyang Liu1, Myungji Kim1, Hong Koo Kim2
1Department of Electrical and Computer Engineering and Petersen Institute of NanoScience and Engineering, 1238 Benedum, University of Pittsburgh, Pittsburgh, PA, 15261, USA.
Scientific Reports
|May 11, 2018
Summary
Electrically induced micro-explosions in graphene/SiO2/Si structures fragment analytes for chip-scale atomic emission spectroscopy. Damage patterns differ based on silicon type, guiding optimization for sensitive, low-voltage analysis.
Area of Science:
- Materials Science
- Nanotechnology
- Spectroscopy
Background:
- Metal-insulator-semiconductor (MIS) structures enable electrically triggered micro-explosions for analyte fragmentation.
- Chip-scale atomic emission spectroscopy (AES) requires efficient atomization methods.
Purpose of the Study:
- Investigate micro-explosion mechanisms in graphene/SiO2/Si (GOS) structures.
- Understand damage morphology differences between n-Si and p-Si substrates.
- Optimize GOS structures for chip-scale AES.
Main Methods:
- Fabrication of graphene/SiO2/Si (GOS) structures.
- Application of high-field pulsed voltage drive under inversion and accumulation bias.
- Analysis of micro-explosion damage morphology using microscopy.
Main Results:
- Micro-explosions occur more readily under inversion bias.
- n-Si GOS shows localized, cone-shaped Si melt explosions.
- p-Si GOS exhibits shallow, laterally spreading trenches in SiO2/Si.
- Damage morphology is linked to carrier multiplication processes.
Conclusions:
- Carrier multiplication mechanisms dictate micro-explosion behavior in GOS structures.
- Findings provide insights for designing GOS-based atomizers for chip-scale AES.
- Optimization can lead to low-voltage, high-sensitivity analysis of small analyte volumes.
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