fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs

Area of Science:

• Artificial Intelligence
• Computer Engineering
• Hardware Acceleration

Background:

• Convolutional Neural Networks (ConvNets) excel in AI tasks but require efficient hardware deployment.
• Field-Programmable Gate Arrays (FPGAs) offer customizable, power-efficient platforms for AI acceleration.
• The growing complexity of ConvNets creates a vast design space for FPGA implementation.

Purpose of the Study:

• To present fpgaConvNet, an end-to-end framework for optimizing ConvNet mapping onto FPGAs.
• To enable efficient navigation of the ConvNet-to-FPGA architectural design space.
• To co-optimize hardware designs for specific ConvNet workloads, target devices, and performance metrics.

Main Methods:

• Utilizes the synchronous dataflow (SDF) paradigm for automated design methodology.
• Employs a set of SDF transformations to explore the architectural design space.
• Implements a systematic multiobjective optimization formulation for hardware generation.

Main Results:

• Generated FPGA designs offer up to 6.65x performance improvement over optimized GPU designs under similar power constraints.
• Achieved up to 2.94x higher performance density compared to state-of-the-art FPGA-based ConvNet architectures.
• Demonstrates efficient co-optimization for ConvNet workload, target device, and application performance.

Conclusions:

• The fpgaConvNet framework provides an effective solution for deploying complex ConvNets on FPGAs.
• The methodology enables significant performance and efficiency gains for AI hardware acceleration.
• Offers a scalable approach to address the challenges of ConvNet-to-FPGA design space exploration.