Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud.

Area of Science:

• Computer Engineering
• Hardware Architecture
• Network-on-Chip Design

Background:

• Cloud services and deep learning (DL) demand more efficient, scalable hardware.
• Current systems face pressure for increased performance-to-power ratios.
• Adaptable, modular interconnects are needed for data centers (DCs) and edge computing.

Purpose of the Study:

• To propose a scalable Software Defined Network-on-Chip (SDNoC) architecture.
• To enhance adaptability and modularity for diverse computing environments (cloud to edge).
• To improve resource partitioning and support data-driven execution models for DL applications.

Main Methods:

• Developed a modular SDNoC architecture merging hierarchical (ring/2D-mesh) and dynamic reconfiguration.
• Integrated customized instructions for data-driven program execution model (PXM) and high-level language mapping.
• Compared the proposed architecture against a conventional flattened 2D-mesh interconnection on FPGA devices.

Main Results:

• Achieved a 9.5% increase in data traffic throughput.
• Reduced average packet latency by 2.2x compared to flattened 2D-mesh.
• Demonstrated low power and resource consumption, confirming good scalability.

Conclusions:

• The proposed SDNoC architecture offers significant performance improvements for cloud and edge computing.
• Its modular and reconfigurable design effectively supports diverse applications, including DL.
• The architecture provides a scalable and energy-efficient solution for future hyperscale systems.