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Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm
Mahmoud T El-Hadidi1, Hany M Elsayed1, Karim Osama1
1Department of Electronics and Electrical Communications Engineering, Faculty of Engineering, Cairo University, Giza 12613, Egypt.
Journal of Advanced Research
|July 27, 2018
Summary
Optimizing a crypto processor involved multi-objective genetic algorithms. Synchronous designs significantly outperform asynchronous ones in delay and energy for security applications like AES.
Area of Science:
- Computer Engineering
- Hardware Security
- Algorithm Optimization
Background:
- Previous work proposed a four-region synchronous architecture for a programmable data-flow crypto processor.
- Security applications demand efficient and optimized cryptographic hardware.
Purpose of the Study:
- To optimize a novel programmable data-flow crypto processor for security applications.
- To formulate the selection of synchronous regions and functional unit distribution as a multi-objective optimization problem.
Main Methods:
- Utilized a modified version of the Non-dominated Sorting Genetic Algorithm II (NSGA-II).
- Integrated the NSGA-II with a component database and a processor emulator.
- Evaluated objective functions: implementation area, execution delay, and energy consumption using the AES algorithm.
Main Results:
- Asynchronous designs incur significant delays (311% more) and energy consumption (308% more) compared to synchronous counterparts.
- Identified the Instruction Region as a key design bottleneck.
- Pareto fronts showed optimal solutions with 4 regions for minimal delay and 7 regions for minimal area/energy in the synchronous case.
Conclusions:
- Synchronous processor designs are superior for delay and energy efficiency in cryptographic applications.
- A minimum-delay design was selected for hardware implementation and verified on FPGA for AES and RC6 algorithms.
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