p-GaAs Nanowire Metal-Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

Area of Science:

• Semiconductor Physics
• Nanotechnology
• Materials Science

Background:

• III-V complementary metal-oxide semiconductor (CMOS) electronics face challenges with p-type transistors and gate insulator charge-trapping.
• Existing technologies struggle to achieve high performance and reliability in these areas.

Purpose of the Study:

• To develop an improved p-type transistor for III-V CMOS electronics.
• To overcome the limitations of gate insulators and enhance device performance.

Main Methods:

• Fabrication of a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET).
• Utilizing the Schottky barrier at the metal-GaAs interface to eliminate the need for a gate insulator.
• Engineering the nanowire structure with an undoped core and a doped shell, with selective etching at gate locations.

Main Results:

• The p-GaAs nanowire MESFET demonstrated superior performance compared to the best p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET).
• Achieved a subthreshold swing of 62 mV/dec (near thermal limit), on-off ratio of ~10^5, and on-resistance of ~700 kΩ.
• Exhibited high-fidelity AC operation up to 10 kHz with a peak transconductance of 1.2 μS/μm.

Conclusions:

• The developed p-GaAs nanowire MESFET offers a promising alternative for high-performance III-V electronics.
• This approach simplifies fabrication and enhances performance by eliminating gate insulators.
• Paves the way for all-GaAs nanowire MESFET complementary circuits.