A debug scheme to improve the error identification in post-silicon validation.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Semiconductor Device Physics

Background:

• Post-silicon validation is crucial for detecting errors missed in pre-silicon verification and manufacturing.
• Increasing design complexity escalates debug time due to the need for more debug data.
• Current methods face challenges in efficiently identifying errors with reduced debug data.

Purpose of the Study:

• To present a novel debug scheme that enhances error identification capabilities in semiconductor post-silicon validation.
• To reduce the volume of debug data required for effective error localization.
• To improve the efficiency of the debug process in complex semiconductor designs.

Main Methods:

• A debug scheme employing hierarchical multiple-input signature registers (MISRs) to concurrently generate three types of signatures.
• Identification of error-suspect debug cycles by analyzing common cycles across the three MISR signatures.
• Real-time comparison of high-level MISR signatures with golden signatures to minimize debug data.
• Utilizing tag bits from high-level MISR results to manage the remaining two MISRs.

Main Results:

• The proposed debug structure significantly improves error identification capability.
• The approach effectively reduces the amount of debug data required compared to previous methods.
• Experimental results validate the enhanced performance and efficiency of the new debug scheme.

Conclusions:

• The developed debug scheme offers a superior method for post-silicon validation error identification.
• This approach provides a more efficient way to handle debug data in complex semiconductor designs.
• The hierarchical MISR-based strategy represents a significant advancement in semiconductor debug technology.