CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Miniaturization of electronic components is crucial for advanced computing.
• Developing novel NEMS devices requires scalable and cost-effective fabrication methods.

Purpose of the Study:

• To demonstrate the feasibility of fabricating copper nanoelectromechanical (NEMS) relays using commercial complementary metal-oxide-semiconductor (CMOS) technology.
• To achieve record-small dimensions and high performance in NEMS switches.

Main Methods:

• Utilized an intra-CMOS-MEMS (complementary metal-oxide-semiconductor - microelectromechanical systems) approach.
• Employed a commercial ST 65 nm CMOS technology for fabrication.
• Characterized contact-mode nano-electromechanical switches.

Main Results:

• Achieved low operating voltage (5.5 V) and a high ON/OFF current ratio (10³).
• Demonstrated an abrupt subthreshold swing of 4.3 mV/decade.
• Fabricated switches with minimum dimensions of 3.50 μm × 100 nm × 180 nm and a 100 nm gap.
• Reported the smallest operable cell area of 0.7 μm² using a top-down fabrication approach.

Conclusions:

• Successfully demonstrated the integration of copper NEMS relays within a commercial CMOS process.
• The developed NEMS switches offer excellent performance metrics and unprecedented miniaturization.
• This work paves the way for highly integrated NEMS-CMOS systems.