Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

Area of Science:

• Microelectromechanical Systems (MEMS)
• Integrated Circuit Design
• Sensor Technology

Background:

• MEMS accelerometers are crucial for motion sensing applications.
• Achieving low noise and minimal zero-g offset in monolithic designs presents significant engineering challenges.
• Standard CMOS processes offer a path for integrating MEMS devices with readout electronics.

Purpose of the Study:

• To present a monolithic CMOS/MEMS accelerometer with low noise and low zero-g offset.
• To detail the design and implementation of a novel readout scheme.
• To validate the performance through experimental measurements.

Main Methods:

• Utilized a standard 0.18 μm CMOS mixed-signal UMC process for monolithic integration.
• Developed a low-noise chopper architecture and a telescopic topology for the readout circuit.
• Implemented a zero-g trimming circuit to minimize initial offset errors.

Main Results:

• Achieved a low noise floor of 421.70 μg/√Hz.
• Demonstrated a system sensitivity of 470 mV/g.
• Reduced the zero-g offset from 1242.63 mg to a mere 2.30 mg.
• Maintained low power consumption at approximately 1.67 mW.

Conclusions:

• The monolithic CMOS/MEMS accelerometer effectively addresses low noise and low offset requirements.
• The developed chopper architecture and telescopic topology are key to achieving high performance.
• The integrated zero-g trimming circuit significantly enhances the accelerometer's accuracy and usability.